Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 347)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 347
12 DMC 1 Command.
0: DMC read access
1: DMC write access 0 SPP: r/w
13 Reserved 0 r
14 DMC 1 Access Abort. Flag
0: DMC SPI Slave access normal termination
1: DMC SPI Slave didn't response 0 SPP: r
15 DMC SPI Busy Bit:
0: Ready for next read or write access
1: Busy. The DMC SPI interface is still active. 0 SPP: r
Table 8-161 DMC 1 SPI LS Word Data Register
Address: 0xC2 -0xC3
Bit Description Default Access
15:0 DMC 1 SPI LS Word Write Data Register.
Contains the write bits 15:0 for a DMC register write access - SPP: w
DMC 1 SPI LS Word Read Data Register.
Contains the data bits 15:0 of the selected DMC 32 bit register
when the DMC SPI access has terminated successfully.
Note: Read DMC 1 SPI LS Word Data Register content as long SPI
access not started. 0 SPP: r
Table 8-160 DMC 1 SPI Control Register (continued)
Address: 0xC0 -0xC1
Bit Description Default Access