Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 269)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 269
INDEX and DATA ports.
The desired configuration registers are accessed in two steps:
1. Write the index of the Logical Device Number Configuration Register (i.e., 07) to the INDEX
PORT and then write the number of the desired logical device to the DATA PORT.
2. Write the address of the desired configuration register within the logical device to the
INDEX PORT and then write or read the configuration register through the DATA PORT.
 Super IO Configuration Registers
Address locations that are not listed are considered reserved register locations. Reads to
reserved registers may return non-zero values. Writes to reserved locations may cause
system failure.
 Global Control Configuration Registers
If accessing the Global Configuration Registers, step 1 is not required. The Super IO returns
to the RUN State.
Only two states are defined (Run and Configuration). In the Run State the Super IO is always
ready to enter the Configuration State.