Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 414)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 414
8.4.2.7.8 DSP Host Event Interrupt Status Mask Register
Address: 0xAE, DspHevStaMaskReg
Width: 16 bit
The bits of this register mask the bits of the DspHevStaReg for the generation of the Host Event
Interrupt (HOUT).
Table 8-207 DSP Host Event Interrupt Status Mask Register
Bit Acronym Type Description Default Pwr Soft
15...10 - - reserved undef - -
9 DspHevIntrptMask9 RW 0b1: DspHevIntrptEnable9,
enables DspHev9 interrupt
generation 0b0 X X
8 DspHevIntrptMask8 RW 0b1: DspHevIntrptEnable8,
enables DspHev8 interrupt
generation 0b0 X X
7 DspHevIntrptMask7 RW 0b1: DspHevIntrptEnable7,
enables DspHev7 interrupt
generation 0b0 X X
6 DspHevIntrptMask6 RW 0b1: DspHevIntrptEnable6,
enables DspHev6 interrupt
generation 0b0 X X
5 DspHevIntrptMask5 RW 0b1: DspHevIntrptEnable5,
enables DspHev5 interrupt
generation 0b0 X X
4 DspHevIntrptMask4 RW 0b1: DspHevIntrptEnable4,
enables DspHev4 interrupt
generation 0b0 X X
3 DspHevIntrptMask3 RW 0b1: DspHevIntrptEnable3,
enables DspHev3 interrupt
generation 0b0 X X
2 DspHevIntrptMask2 RW 0b1: DspHevIntrptEnable2,
enables DspHev2 interrupt
generation 0b0 X X