Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 334)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 334
 Cascade Interrupt Registers
Table 8-140 Cascade Interrupt Status Register
Address: 0x92 - 0x93
Bit Interrupt Signal Description Default Access
0 DMC_CONF_CRC_ERR DMC Base signals a critical error Ext. SPP: r
1 DMC_HOUT_DSP_ DMC Base signals host interrupt Ext. SPP: r
2 DMC_PWRGD DMC Base power good fail Ext. SPP: r
3 - Reserved 0 r
4 DMC1_CONF_CRC_ERR DMC 1 signals a critical error Ext. SPP: r
5 DMC1_HOUT_DSP_ DMC 1 signals host interrupt Ext. SPP: r
6 DMC1_PWRGD DMC 1 power good fail Ext. SPP: r
7 - Reserved 0 r
8 DMC2_CONF_CRC_ERR DMC 2 signals a critical error Ext. SPP: r
9 DMC2_HOUT_DSP_ DMC 2 signals host interrupt Ext. SPP: r
10 DMC2_PWRGD DMC 2 power good fail Ext. SPP: r
11 - Reserved 0 r
12 RTM_CONF_CRC_ERR ARTM Configuration Error. SED Ext. SPP: r
15:13 - Reserved for ARMT 0 r
Table 8-141 Cascade Interrupt Enable Register
Address: 0x94 - 0x95
Bit Interrupt Signal Description Default Access
0 DMC_CONF_CRC_ERR DMC Base signals a critical error
enable.
0: Disabled
1:Enabled 0 SPP: r/w