Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 412)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 412
The bits of this register reset the respective bits in DspHevStaReg. Writing a 1 to a bit in
DspHevStaResReg resets the corresponding bit in DspHevStaReg. The interrupt bit in
DspHevStaReg is kept reset until writing a 0 to the corresponding bit in DspHevStaResReg
reenables its monitor function.again.
8.4.2.7.7 DSP Watchdog Interrupt Status Mask Register
Address: 0xAC, DspWdgStaMaskReg
Width: 16 bit
Table 8-205 DSP Host Event Interrupt Status Reset Register
Bit Acronym Type Description Default Pwr Soft
15...10 - - reserved undef - -
9 DspHevRes9 RW 0b1: DspHevRes9, resets DspHev9 bit
in DspHevWdgStaReg 0b0 X X
8 DspHevRes8 RW 0b1: DspHevRes8, resets DspHev8 bit
in DspHevWdgStaReg 0b0 X X
7 DspHevRes7 RW 0b1: DspHevRes7, resets DspHev7 bit
in DspHevWdgStaReg 0b0 X X
6 DspHevRes6 RW 0b1: DspHevRes6, resets DspHev6 bit
in DspHevWdgStaReg 0b0 X X
5 DspHevRes5 RW 0b1: DspHevRes5, resets DspHev5 bit
in DspHevWdgStaReg 0b0 X X
4 DspHevRes4 RW 0b1: DspHevRes4, resets DspHev4 bit
in DspHevWdgStaReg 0b0 X X
3 DspHevRes3 RW 0b1: DspHevRes3, resets DspHev3 bit
in DspHevWdgStaReg 0b0 X X
2 DspHevRes2 RW 0b1: DspHevRes2, resets DspHev2 bit
in DspHevWdgStaReg 0b0 X X
1 DspHevRes1 RW 0b1: DspHevRes1, resets DspHev1 bit
in DspHevWdgStaReg 0b0 X X
0 DspHevRes0 RW 0b1: DspHevRes0, resets DspHev0 bit
in DspHevWdgStaReg 0b0 X X