Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 427)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 427
8.4.2.11 General Test Registers (GenTestRegs)
Resets:
Pwr = Power On Reset
Soft = Soft Reset
General Test Registers
8.4.2.11.1 Fault Insertion Register
Address: 0xE0, FltInsrtReg
Width: 32 bit
Allows simulating several faults initiated not by the original source but by the host SW for test
purposes
8.4.2.11.2 ScratchPad Register
Address: 0xE4, ScratchPadReg
Width: 8 bit
Table 8-223 Fault Insertion Register
Bit Acronym Type Description Default Pwr Soft
31...8 FltInsMgckNmb W Magic number to allow write
execution
0xFAAFA5: FltInsMgckNmb, Magic
number, SoftError is only provoked
if this bits are written
simultaneously with this value undef - -
7...1 - - reserved undef - -
0 SoftErrorPrvk W Provoke soft error
0b1: SoftErrorPrvk, A soft error of
the Fpga internal configuration
SRAM (monitored continuously for
CRC checks in background by HW)
is faked. undef - -