Artesyn ATCA-8310 Installation and Use (May 2014) - Manual (Page 339)

CPLD and FPGA
ATCA-8310 Installation and Use (6806800M72E) 339
Table 8-148 Telecom Clocking Interrupt Enable Register
Address: 0xA2 - 0xA3
Bit Interrupt Name Description Default Access
0 ACS8520_IRQ Interrupt from device ACS8520
enable:
0: Disabled
1:Enabled 0 SPP: r/w
1 CLK_MONITOR_FINISHED Interrupt from Telecom Clock
supervision enable. Single Mode:
0: Disabled
1:Enabled 0 SPP: r/w
2 CLK_MONITOR_OUT_OF_
RANGE Interrupt from Telecom Clock
supervision enable. Out of Range
Mode:
0: Disabled
1:Enabled 0 SPP: r/w
15:3 - Reserved 0 r