NEC Network Controller uPD98502 - Manual (Page 90)

CHAPTER 2 V R 4120A
90 Preliminary User’s Manual S15543EJ1V0UM
2.3.4.3 Branch on equal instruction (BEQ rs, rt, offset)
IF stage Same as the IF stage for the ADD instruction.
IT stage Same as the IT stage for the ADD instruction.
RF stage During
Φ2, the register file is addressed with the rs and rt fields. A check is performed to
determine if each corresponding bit position of these two operands has equal values. If they
are equal, the PC is set to PC + target, where target is the sign-extended offset field. If they are
not equal, the PC is set to PC + 4.
EX stage The next PC resulting from the branch comparison is valid at the beginning of Φ2 for instruction
fetch.
DC stage This stage is a NOP for this instruction.
WB stage This stage is a NOP for this instruction.
Figure 2-15. BEQ Instruction Pipeline Activities (In MIPS III Instruction Mode)
IF1 Cycle
Phase
PCycle
PClock
IF2
Φ2 Φ1 Φ2 Φ1 Φ2 Φ1 Φ2 Φ1 Φ2 Φ1
RF1 RF2 EX1 EX2 DC1 DC2 WB1 WB2
ITLB
IDC
ITC
ICA
IDEC EX
BAC
RF