Ddivu, Doubleword divide unsigned – NEC Network Controller uPD98502 User Manual

Page 474

APPENDIX A MIPS III INSTRUCTION SET DETAILS

474

Preliminary User’s Manual S15543EJ1V0UM

DDIVU

Doubleword Divide Unsigned

DDIVU

SPECIAL

0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0

26 25

21 20

16 15

DDIVU

0 1 1 1 1 1

6 5

Format:

DDIVU rs, rt

Description:

The contents of general register

rs are divided by the contents of general register rt, treating both operands as

unsigned values. No integer overflow exception occurs under any circumstances, and the result of this operation is

undefined when the divisor is zero.

This instruction may be followed by additional instructions to check for a zero divisor, inserted by the programmer.

When the operation completes, the quotient word of the double result is loaded into special register

LO, and the

remainder word of the double result is loaded into special register

HI.

If either of the two preceding instructions is MFHI or MFLO, the results of those instructions are undefined. Correct

operation requires separating reads of

HI or LO from writes by two or more instructions.

This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or

supervisor mode causes a reserved instruction exception.

Operation:

T-2:

← undefined

T-1:

← undefined

← (0 || GPR [rs]) div (0 || GPR [rt])

← (0 || GPR [rs]) mod (0 || GPR [rt])

Exceptions:

Reserved instruction exception (32-bit user mode/supervisor mode)