NEC Network Controller uPD98502 - Manual (Page 272)

CHAPTER 4 ATM CELL PROCESSOR
272 Preliminary User’s Manual S15543EJ1V0UM
CLP Set to a 1 if the CLP in the header of at least one cell of the packets being
received is equal to a 1.
BFA Set to a 1 if the free buffer assigned to this VC exists.
RID Set to a 1 if an error occurs while a packet is being received. Then, the
subsequent cells of the packet, including the last cell, are discarded.
DD If a free buffer is not assigned, the cell is discarded and this field is set to a 1.
DP Always a 0 because it is not used by ATM Cell Processor.
MB Mailbox number.
POOL No. Pool number. (ATM Cell Processor supports pool numbers 0 to 7.)
UINFO User information
T1 TIMESTAMP Area used for T1 timer calculation
CI Congestion notification.
OD OAM cell reception/discard indication bit.
A/R AAL-5/RAW cell reception indication bit.
MAX. No. OF BYTES Maximum number of bytes in one packet
REMAINING WORDS IN CURRENT
BUFFER
Number of words of the free area remaining in the current buffer
CURRENT COUNT OF BYTES Number of bytes of the current packet that have been received so far
CRC-32 COUNT Used for CRC-32 value calculation
BUFFER WRITE ADDRESS Next address in the currently assigned free buffer that is used for storage
CURRENT BUFFER POINTER Start address of the free buffer to be assigned next time.
PACKET START ADDRESS Start address of the packet (start address of the batch assigned first)
WORD 6 to WORD 12 These fields are used internally.
BACKWARD POINTER VC Number of the VC linked before this VC in the T1 link list
LST Set to a 1 if the VC is the last one linked in the T1 link list.
FORWARD POINTER VC Number of the VC linked after this VC in the T1 link list
4.8.3.2 Non AAL-5 traffic support
Every time ATM Cell Processor receives a raw cell, it makes a raw cell data with 53 byte raw cell and 11 byte
indication and stores it to the appropriate Rx pool. Then, ATM Cell Processor sets corresponding bits in A_GSR
register and issues an interruption if not masked.
Since ATM Cell Processor treats raw cells as a unit of cell not a packet, it doesn’t set rx indications in Rx mailbox.
When ATM Cell Processor receives raw cells, CRC-10 verify function is always enable. If ATM Cell Processor detects
CRC-10 error, sets error bit in raw cell data.
(1) OAM F5 cell
When OD bit in VC table is a 1 and PTI field in received ATM cell header is “1xx”, ATM Cell Processor generates
Raw cell data and stores it in pool 0. It sets PCR0=1 in A_GSR register and issues an interruption to V
R
4120A, if not
masked. ATM Cell Processor always stores these data in Pool 0. If OD bit is set to a 1, Pool 0 has to be set for Raw
cell data.
(2) Non AAL-5 traffic
When A/R bit in VC table is a 0, ATM Cell Processor treats received cells that belong to the VC as raw cells. If
receives raw cells, ATM Cell Processor has to assign a pool to raw cell data.
(3) Raw cell data
The following is the Raw cell data format in little endian mode.