NEC Network Controller uPD98502 - Manual (Page 496)

APPENDIX A MIPS III INSTRUCTION SET DETAILS
496 Preliminary User’s Manual S15543EJ1V0UM
HIBERNATE
Hibernate
HIBERNATE
CO
1
COP0
0 1 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HIBERNATE
1 0 0 0 1 1
31 26 25 24 6 5 0
6 1 19 6
Format:
HIBERNATE
Description:
HIBERNATE instruction starts mode transition from Fullspeed mode to Hibernate mode.
When the HIBERNATE instruction finishes the WB stage, the processor wait by the SysAD bus is idle state, after
then the internal clocks and the system interface clocks will shut down, thus freezing the pipeline.
Cold Reset causes the Hibernate mode to the Fullspeed mode transition.
Operation:
32, 64 T:
T+1: Hibernate operation ()
Exceptions:
Coprocessor unusable exception