NEC Network Controller uPD98502 - Manual (Page 121)

CHAPTER 2 V R 4120A
Preliminary User’s Manual S15543EJ1V0UM 121
Table 2-32. Cache Algorithm
C Bit Value Cache Algorithm
0 Cached
1 Cached
2 Uncached
3 Cached
4 Cached
5 Cached
6 Cached
7 Cached
2.4.5.4 PageMask register (5)
The PageMask register is a read/write register used for reading from or writing to the TLB; it holds a comparison
mask that sets the page size for each TLB entry, as shown in Table 2-33. Page sizes must be from 1 Kbyte to 256
Kbytes.
TLB read and write instructions use this register as either a source or a destination; Bits 18 to 11 that are targets of
comparison are masked during address translation.
Figure 2-37. Page Mask Register
18 19 0 31 11 10
0 MASK 0
13 8 11
MASK : Page comparison mask, which determines the virtual page size for the corresponding entry.
0
: RFU. Write 0 in a write operation. When this field is read, 0 is read.
Table 2-33 lists the mask pattern for each page size. If the mask pattern is one not listed below, the TLB behaves
unexpectedly.
Table 2-33. Mask Values and Page Sizes
Page Size Bit
18 17 16 15 14 13 12 11
1 Kbyte 0 0 0 0 0 0 0 0
4 Kbytes 0 0 0 0 0 0 1 1
16 Kbytes 0 0 0 0 1 1 1 1
64 Kbytes 0 0 1 1 1 1 1 1
256 Kbytes 1 1 1 1 1 1 1 1