NEC Network Controller uPD98502 - Manual (Page 202)

CHAPTER 3 SYSTEM CONTROLLER
202 Preliminary User’s Manual S15543EJ1V0UM
Table 3-1. Endian Configuration Table
BIG pin ENDCEN
pin
Status register
RE field in V R 4120A
Endian
in V R 4120A
Endian
in system controller
Endian converter
operation
0 0 0 LITTLE LITTLE Transparent
0 1 0 LITTLE LITTLE Transparent
1 0 0 BIG LITTLE Data swap mode
1 1 0 BIG LITTLE Address swap mode
Remark V R 4120A does not support reverse endian mode.
Table 3-2. Endian Translation Table in Endian Converter
CPU access type BIG ENDCEN Before translation
SysAD[1:0]
After translation
SysAD[1:0]
Notes
2-word
4-word
1 1 00 00 Valid
01 01 Invalid
10 10 Invalid
Block
11 11 Invalid
00 11 Valid
01 10 Valid
10 01 Valid
Single 1-byte 1 1
11 00 Valid
00 10 Valid
01 11 Invalid
10 00 Valid
Single 2-byte 1 1
11 01 Invalid
00 01 Valid
01 00 Valid
10 11 Invalid
Single 3-byte 1 1
11 10 Invalid
00 00 Valid
01 01 Invalid
10 10 Invalid
Single 4-byte 1 1
11 11 Invalid
CPU access type BIG ENDCEN Before translation
SysAD[1:0]
After translation
SysAD[1:0]
Note
Any 1 0 [31:24][23:16][15:8][7:0] [7:0][15:8][23:16][31:24] Byte swap