NEC Network Controller uPD98502 - Manual (Page 201)

CHAPTER 3 SYSTEM CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 201
3.3 CPU Interface
The system controller provides the direct interface for the V
R
4120A using the 32-bit SysAD bus operated at
100 MHz or 66 MHz.
3.3.1 Overview
• Connects to the V
R 4120A CPU bus “SysAD bus” directly.
• Supports all V
R
4120A bus cycles at 66 MHz or 100 MHz.
• Supports data rate D only.
• Supports sequential ordering only.
• 4-word (16-byte) x 4-entry write command buffer.
• Little-endian or big-endian byte order.
• Not support 8-word burst R/W on SysAD bus
3.3.2 Data rate control
The V R 4120A-to-system controller data rate is programmable by setting the EP field (bits 27:24) of the
configuration register in the V R 4120A. The controller supports only data rate D. Thus this block does not support AD
mode.
3.3.3 Burst size control
This block - to - V R 4120A burst data size is determined by the OSysCMD[2:0] signal on SysAD bus. It is
programmable in the IB bit (bits 5) of the V R 4120A’s Configuration Register (Please see the section 2.4.5.8 Config
register (16)). The
µPD98502 support 4-word burst mode only. Please set “0” to IB bit of V
R 4120’s Configuration
Register.
3.3.4 Address decoding
The controller latches the address on the SysAD bus. It then decodes the address and SysCmd signals to
determine the transaction type. Ten address ranges can be decoded:
• One range for external boot PROM or flash.
• One range for external SDRAM.
• One range for system controller’s internal configuration registers.
Boot PROM/flash is mapped according to its size. System controller’s internal registers are fixed at base address
1000_0000H, to allow the V R 4120A to access them during boot, before they have been configured. All other decode
ranges are programmable.
3.3.5 Endian conversion
The BE bit in the configuration register in the V R 4120A specifies the byte ordering at reset. BE = 0 configures little-
endian order, BE = 1 configures big-endian order. The endian mode is controlled by “BIG” signal. V R 4120A interface
of the system controller supports both big- and little-endian byte ordering on the SysAd bus by using endian converter.
All of the other interfaces in the system controller operate only in little-endian mode.
When the V
R
4120A is operated in the big-endian mode (external BIG pin is high), the system controller provides
the two endian conversion methods controlled by external ENDCEN pin. If ENDCEN pin is low, the system controller
performs the data swap on the SysAD bus (see Table 3-2. Endian Translation Table in Endian Converter for data
swap mode). If ENDCEN pin is high, the system controller performs the address swap on the SysAD bus (the detail is
described in the Table 3-2. Endian Translation Table in Endian Converter for the address swap mode).