NEC Network Controller uPD98502 - Manual (Page 560)

APPENDIX A MIPS III INSTRUCTION SET DETAILS
560 Preliminary User’s Manual S15543EJ1V0UM
SUSPEND
Suspend
SUSPEND
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
COP0
0 1 0 0 0 0
SUSPEND
1 0 0 0 1 0
31 26 25 6 5 0
6 19 6
CO
1
1
24
Format:
SUSPEND
Description:
SUSPEND instruction starts mode transition from Fullspeed mode to Suspend mode.
When the SUSPEND instruction finishes the WB stage, this processor wait by the SysAD bus is idle state, after
then the internal clocks including the TClock will shut down, thus freezing the pipeline. The PLL, Timer/Interrupt
clocks and MasterOut, will continue to run.
Once this processor is in Suspend mode, any interrupt, including the internally generated timer interrupt, NMI, Soft
Reset and Cold Reset will cause this processor to exit Suspend mode and to enter Fullspeed mode.
Operation:
32, 64 T:
T+1: Suspend Operation ()
Exceptions:
Coprocessor unusable exception
Remark Refer to Section 2.6.3.1 Power modes for details about the operation of the peripheral units at mode
transition.