NEC Network Controller uPD98502 - Manual (Page 220)

CHAPTER 3 SYSTEM CONTROLLER
220 Preliminary User’s Manual S15543EJ1V0UM
3.4.18 SDRAM memory initialization
The following sections describe the configuration sequence used in this initialization.
3.4.1.1 Power-on initialization sequence by memory controller
The following sequence to configure memory is done automatically after reset:
1. Waits for 100
µs after power-on.
2. Performs all bank precharges.
3. Performs eight sequential auto refreshes (CBR).
3.4.1.2 Memory initialization sequence using software
The SDRAM must be initialized by the software using following sequence after power-on initialization.
1. Program the SDRAM type selection register “SDTSR”
2. Program the SDRAM mode register “SDMDR”.
3. Wait for 20
µs.
4. Program the DRAM refresh counter register.
At this point, memory is ready to use. All other configuration registers in the controller should then be programmed
before commencing normal operation.
Remark The software should not change the SDTSR and SDMDR after SDRAM initialization sequence