NEC Network Controller uPD98502 - Manual (Page 101)

CHAPTER 2 V R 4120A
Preliminary User’s Manual S15543EJ1V0UM 101
2.4 Memory Management System
The V R 4120A Core provides a memory management unit (MMU) which uses a translation lookaside buffer (TLB) to
translate virtual addresses into physical addresses. This chapter describes the virtual and physical address spaces,
the virtual-to-physical address translation, the operation of the TLB in making these translations, and the CP0
registers that provide the software interface to the TLB.
2.4.1 Translation lookaside buffer (TLB)
Virtual addresses are translated into physical addresses using an on-chip TLB
Note
. The on-chip TLB is a fully-
associative memory that holds 32 entries, which provide mapping to odd/even page in pairs for one entry. These
pages can have five different sizes, 1 K, 4 K, 16 K, 64 K, and 256 K, and can be specified in each entry. If it is
supplied with a virtual address, each of the TLB entries is checked simultaneously to see whether they match the
virtual addresses that are provided with the ASID field and saved in the EntryHi register.
If there is a virtual address match, or “hit,” in the TLB, the physical page number is extracted from the TLB and
concatenated with the offset to form the physical address.
If no match occurs (TLB “miss”), an exception is taken and software refills the TLB from the page table resident in
memory. The software writes to an entry selected using the Index register or a random entry indicated in the Random
register.
If more than one entry in the TLB matches the virtual address being translated, the operation is undefined and the
TLB may be disabled. In this case, the TLB-Shutdown (TS) bit of the status register is set to 1, and the TLB becomes
unusable (an attempt to access the TLB results in a TLB Mismatch exception regardless of whether there is an entry
that hits). The TS bit can be cleared only by a reset.
Note Depending on the address space, virtual addresses may be converted to physical addresses without using
a TLB. For example, address translation for the kseg0 or kseg1 address space does not use mapping.
The physical addresses of these address spaces are determined by subtracting the base address of the
address space from the virtual addresses.