NEC Network Controller uPD98502 - Manual (Page 166)

CHAPTER 2 V R 4120A
166 Preliminary User’s Manual S15543EJ1V0UM
2.6.3.1 Power modes
The V R 4120A supports four power modes: Fullspeed mode, Standby mode, Suspend mode, and Hibernate mode.
(1) Fullspeed mode
This is the normal operation mode.
The V R 4120A’s default status sets operation under Fullspeed mode. After the processor is reset, the V R 4120A
returns to Fullspeed mode.
(2) Standby mode
When a STANDBY instruction has been executed, the processor can be set to Standby mode. During Standby
mode, all of the internal clocks in the CPU core except for the timer and interrupt clocks are held at high level.
The peripheral units all operate as they do during Fullspeed mode. This means that DMA operations are enabled
during Standby mode.
When the STANDBY instruction completes the WB stage, the V R 4120A remains idle until the SysAD internal bus
enters the idle state. Next, the clocks in the CPU core are shut down and pipeline operation is stopped.
However, the PLL, timer, and interrupt clocks continue to operate, as do the internal bus clocks (TClock and
MasterOut).
During Standby mode, the processor is returned to Fullspeed mode if any interrupt occurs, including a timer
interrupt that occurs internally.
(3) Suspend mode
When the SUSPEND instruction has been executed, the processor can be set to Suspend mode. During
Suspend mode, the processor stalls the pipeline and supplying all of the internal clocks in the CPU core except
for PLL timer and interrupt clocks are stopped. The V R 4120A stops supplying TClock to peripheral units.
Accordingly, during Suspend mode peripheral units can only be activated by a special interrupt unit (DCD_B
control, etc.). While in this mode, the register and cache contents are retained.
When the SUSPEND instruction completes the WB stage, the V
R
4120A switches the DRAM to self refresh mode
and then waits for the SysAD internal bus to enter the idle state. Next, the clocks in the CPU core are shut down
and pipeline operation is stopped. The V R 4120A then stops supplying TClock to peripheral units. However, the
PLL, timer, and interrupt clocks continue to operate, as do the MasterOut.
The processor remains in Suspend mode until an interrupt is received, at which time it returns to Fullspeed mode.
(4) Hibernate mode
When the HIBERNATE instruction has been executed, the processor can be set to Hibernate mode. During
Hibernate mode, the processor stops supplying clocks to all units. The register and cache contents are retained
and output of TClock and MasterOut is stopped. The processor remains in Hibernate mode until the POWER pin
is asserted or a WakeUpTimer interrupt occurs at which the processor returns to Fullspeed mode.
In this mode, supplying voltage to the 2.5-V power-supply systems (VDD2, VDDP, VDDPD) can be stopped.
When the voltage of the 2.5-V power supplies becomes 0 V, the power dissipation becomes almost 0 W (it is not
exactly 0 V because there are a 32.768-kHz oscillator and on-chip peripheral circuits operating at 32.768 kHz).