NEC Network Controller uPD98502 - Manual (Page 382)

CHAPTER 7 PCI CONTROLLER
382 Preliminary User’s Manual S15543EJ1V0UM
In the case that the value except for ‘0’ is set to P_RTMR register, the PCI Controller abandons the access when
the number of target retry which the PCI Controller is received for the same access goes over the value in P_RTMR
register. This function is called as “Retry-Timer”. Setting ‘0’ to P_RTMR register disables this function.
7.2.3.2 On Internal bus
(1) Bus Error
When the PCI Controller receives Bus Error on internal bus as master, the PCI Controller sets IRBER bit in
P_IGSR register and PRBER bit in P_PGSR register in read transaction, or sets IWBER bit in P_IGSR register and
PWBER bit in P_PGSR register in write transaction. Then, the PCI Controller issues interrupts to an external PCI-Host
device and the V R 4120A (if not masked). The PCI Controller stops the access, and returns to the state in which the
PCI Controller can accept a new access.
7.2.4 Warning for Deadlocks
The PCI Controller can use Non-Delayed Read rule and Non-Posted Write rule for each direction. In these rules,
the PCI Controller does not release the bus until it completes the transaction on the other bus. Therefore, if the PCI
Controller is set to use Non-Delayed Read rule and Non-Posted Write rule on each buses and transactions are issued
from both buses at the same time, deadlock will occur. It is recommended that either Non-Delayed Read rule or Non-
Posted Write rule is used at one side at least.
The PCI Controller can accept 1 transaction on each bus and for read and write respectively. Once the PCI
Controller accepts a transaction, it issues “retry” for the same kind of the transactions. If the master that has the
highest priority issues the access to the PCI Controller continuously on each bus, the PCI Controller can not
completes the transactions, and deadlock will occur.