NEC Network Controller uPD98502 - Manual (Page 401)

CHAPTER 7 PCI CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 401
7.5.18 P_RTMR (Retry Timer Register)
This register is used to set the limitation of the number of retry repetition. ‘0’ disables this function. See 7.2.3.1 (5)
Received target retry as PCI-master for further details.
R/W Bits Field
Internal
bus
PCI
Default Description
31:0 RTMR R/W R/W 0000_
0000H
Sets the number of retry repetition. ‘0000_0000H’ disables this
function.
7.5.19 P_CONFIG (PCI Configuration Registers)
7.5.19.1 PCI configuration register map
Offset Address
Note
31 24 23 16 15 8 7 0
1000_4100H Device ID Vendor ID
1000_4104H Status Command
1000_4108H Class Code Revision ID
1000_410CH Reserved Header Type Latency Timer Cache Line Size
1000_4110H Window Memory Base Address Register
1000_4114H Register Memory Base Address Register
1000_4118H Reserved
1000_411CH Reserved
1000_4120H Reserved
1000_4124H Reserved
1000_4128H Reserved
1000_412CH Subsystem ID Subsystem Vendor ID
1000_4130H Reserved
1000_4134H Reserved Cap_Ptr
1000_4138H Reserved
1000_413CH Max_Lat Min_Gnt Interrupt Pin Interrupt Line
1000_4140H PMC Next_Item_Ptr Cap_ID
1000_4144H PMData Reserved PMCSR
1000_4148H:
1000_41FCH
Reserved
Note The view from PCI side address is assigned by “Register Memory Base Address Register”.