Shift left logical – NEC Network Controller uPD98502 User Manual
Page 547
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM
547
SLL
Shift Left Logical
SLL
SPECIAL
0 0 0 0 0 0
rt
rd
sa
SLL
0 0 0 0 0 0
31
26 25
21 20
16 15
11 10
6 5
0
6
5
5
5
5
6
0
0 0 0 0 0
Format:
SLL rd, rt, sa
Description:
The contents of general register
rt are shifted left by sa bits, inserting zeros into the low-order bits.
The result is placed in register
rd.
In 64-bit
mode, the 32-bit result is sign-extended when placed in the destination register. It is sign extended for all
shift amounts, including zero; SLL with zero shift amount truncates a 64-bit value to 32 bits and then sign extends
this 32-bit value. SLL, unlike nearly all other word operations, does not require an operand to be a properly sign-
extended word value to produce a valid sign-extended word result.
Operation:
32
T:
GPR [rd]
← GPR [rt]
31 - sa...0
|| 0
sa
64
T:
s
← 0 || sa
temp
← GPR [rt]
31 - s...0
|| 0
s
GPR [rd]
← (temp
31
)
32
|| temp
Exceptions:
None
Caution
SLL with a shift amount of zero may be treated as a NOP by some assemblers, at some
optimization levels. If using SLL with a purpose of sign-extension, check the assembler
specification.