NEC Network Controller uPD98502 - Manual (Page 138)

CHAPTER 2 V R 4120A
138 Preliminary User’s Manual S15543EJ1V0UM
2.5.3.7 Exception program counter (EPC) register (14)
The Exception Program Counter (EPC) is a read/write register that contains the address at which processing
resumes after an exception has been serviced. Because the µPD98502 does not support the MIPS16 instruction
mode, the EPC register contains either:
• Virtual address of the instruction that caused the exception.
• Virtual address of the immediately preceding branch or jump instruction (when the instruction associated with
the exception is in a branch delay slot, and the BD bit in the Cause register is set to 1).
The EXL bit in the Status register is set to 1 to keep the processor from overwriting the address of the exception-
causing instruction contained in the EPC register in the event of another exception.
Figure 2-54 shows the EPC register format.
Figure 2-54. EPC Register Format
(a) 32-bit mode
32
0 31
EPC
(b) 64-bit mode
64
0 63
EPC
EPC: Restart address after exception processing.