NEC Network Controller uPD98502 - Manual (Page 244)

CHAPTER 4 ATM CELL PROCESSOR
244 Preliminary User’s Manual S15543EJ1V0UM
4.4.13 A_MWA0 to A_MWA3 (Mailbox Write Address Register)
A_MWA0 to A_MWA3 shows write address of Receive Mailbox (Mailbox0 and Mailbox1) and Transmit Mailbox
(Mailbox2 and Mailbox3) respectively. Initial value is zero.
Bits Field R/W Default Description
31:0 A_MWA0 R/W 0 Write address of Mailbox0
Bits Field R/W Default Description
31:0 A_MWA1 R/W 0 Write address of Mailbox1
Bits Field R/W Default Description
31:0 A_MWA2 R/W 0 Write address of Mailbox2
Bits Field R/W Default Description
31:0 A_MWA3 R/W 0 Write address of Mailbox3
4.4.14 A_RCC (Valid Received Cell Counter)
A_RCC counts the number of valid received cells. It is a 32-bit counter. Overflow of this counter does NOT cause
any interruption. Initial value is zero.
Bits Field R/W Default Description
31:0 A_RCC R 0 Number of valid received cells
4.4.15 A_TCC (Valid Transmitted Cell Counter)
A_TCC counts the number of valid transmitted cells. It is a 32-bit counter. Overflow of this counter does NOT
cause any interruption. Initial value is zero.
Bits Field R/W Default Description
31:0 A_TCC R 0 Number of valid transmitted cells
4.4.16 A_RUEC (Receive Unprovisioned VPI/VCI Error Cell Counter)
A_RUEC counts the number of received cells with VPI/VCI Error. It is a 32-bit counter. Overflow of this counter
does NOT cause any interruption. Initial value is zero.
Bits Field R/W Default Description
31:0 A_RUEC R 0 Number of received cells with VPI/VCI Error
4.4.17 A_RIDC (Receive Internal Dropped Cell Counter)
A_RIDC counts the number of received cells which are dropped inside ATM Cell Processor. It is a 32-bit counter.
Overflow of this counter does NOT cause any interruption. Initial value is zero.
Bits Field R/W Default Description
31:0 A_RIDC R 0 Number of dropped cells