NEC Network Controller uPD98502 - Manual (Page 504)

APPENDIX A MIPS III INSTRUCTION SET DETAILS
504 Preliminary User’s Manual S15543EJ1V0UM
LD
Load Doubleword
LD
base
LD
1 1 0 1 1 1
rt offset
31 26 25 21 20 16 15 0
6 5 5 16
Format:
LD rt, offset (base)
Description:
The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address.
The contents of the 64-bit doubleword at the memory location specified by the effective address are loaded into
general register rt.
If any of the three least-significant bits of the effective address are non-zero, an address error exception occurs.
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
Operation:
64 T: vAddr ← ((offset
15
) 48 || offset
15..0
) + GPR [base]
(pAddr, uncached)
← AddressTranslation (vAddr, DATA)
data ← LoadMemory (uncached, DOUBLEWORD, pAddr, vAddr, DATA)
GPR [rt] ← data
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
Reserved instruction exception (32-bit user mode/supervisor mode)