NEC Network Controller uPD98502 - Manual (Page 152)

CHAPTER 2 V R 4120A
152 Preliminary User’s Manual S15543EJ1V0UM
2.5.4.9 Bus error exception
(1) Cause
A Bus Error exception is raised by board-level circuitry for events such as bus time-out, local bus parity errors, and
invalid physical memory addresses or access types. This exception is not maskable.
A Bus Error exception occurs only when a cache miss refill, uncached reference, or unbuffered write occurs
simultaneously. In other words, it occurs when an illegal access is detected during BCU read.
For details of illegal accesses.
(2) Processing
The common interrupt vector is used for a Bus Error exception. The IBE or DBE code in the ExcCode field of the
Cause register is set, signifying whether the instruction caused the exception by an instruction reference, load
operation, or store operation.
The EPC register contains the address of the instruction that caused the exception. However, if this instruction is
in a branch delay slot, the EPC register contains the address of the preceding jump or branch instruction, and the
BD bit of the Cause register is set to 1.
(3) Servicing
The physical address at which the fault occurred can be computed from information available in the System
Control Coprocessor (CP0) registers.
• If the IBE code in the Cause register is set (indicating an instruction fetch), the virtual address is contained in
the EPC register.
• If the DBE code is set (indicating a load or store), the virtual address of the instruction that caused the
exception is saved to the EPC register.
The virtual address of the load and store instruction can then be obtained by interpreting the instruction. The
physical address can be obtained by using the TLBP instruction and reading the EntryLo register to compute the
physical page number.
At the time of this exception, the kernel reports the UNIX SIGBUS (bus error) signal to the current process, but the
exception is usually fatal.