NEC Network Controller uPD98502 - Manual (Page 431)

Preliminary User’s Manual S15543EJ1V0UM 431
APPENDIX A MIPS III INSTRUCTION SET DETAILS
This chapter provides a detailed description of the operation of each instruction in both 32- and 64-bit modes. The
instructions are listed in alphabetical order.
A.1 Instruction Notation Conventions
In this chapter, all variable subfields in an instruction format (such as rs, rt, immediate, etc.) are shown in
lowercase names.
For the sake of clarity, we sometimes use an alias for a variable subfield in the formats of specific instructions. For
example, we use base instead of rs in the format for load and store instructions. Such an alias is always lower case,
since it refers to a variable subfield.
Figures with the actual bit encoding for all the mnemonics are located at the end of this chapter (A.6 CPU
Instruction Opcode Bit Encoding), and the bit encoding also accompanies each instruction.
In the instruction descriptions that follow, the operation section describes the operation performed by each
instruction using a high-level language notation. The V R 4120A CPU can operate as either a 32- or 64-bit
microprocessor and the operation for both modes is included with the instruction description.
Special symbols used in the notation are described in Table A-1.