NEC Network Controller uPD98502 - Manual (Page 165)

CHAPTER 2 V R 4120A
Preliminary User’s Manual S15543EJ1V0UM 165
2.6 Initialization Interface
This section describes the reset sequence of the V
R
4120A Core. For details about factors of reset or reset of the
whole V
R
4120A Core.
2.6.1 Cold reset
In the V R 4120A Core, a cold reset sequence is executed in the CPU core in the following cases:
• Hardware reset
• Deadman’s SW shutdown
• Software shutdown
• HAL Timer shutdown
A Cold Reset completely initializes the CPU core, except for the following register bits.
• The TS and SR bits of the Status register are cleared to 0.
• The ERL and BEV bits of the Status register are set to 1.
• The upper limit value (31) is set in the Random register.
• The Wired register is initialized to 0.
• Bits 31 to 28 of the Config register are set to 0 and bits 22 to 3 to 04800H; the other bits are undefined.
• The values of the other registers are undefined.
2.6.2 Soft reset
A Soft Reset initializes the CPU core without affecting the clocks; in other words, a Soft Reset is a logic reset. In a
Soft Reset, the CPU core retains as much state information as possible; all state information except for the following is
retained:
• The TS bit of the Status register is cleared to 0.
• The SR, ERL and BEV bits of the Status register are set to 1.
• The Count register is initialized to 0.
• The IP7 bit of the Cause register is cleared to 0.
• Any Interrupts generated on the SysAD bus are cleared.
• NMI is cleared.
• The Config register is initialized.
2.6.3 V
R
4120A processor modes
The V
R
4120A supports various modes, which can be selected by the user. The CPU core mode is set each time a
write occurs in the Status register and Config register. The on-chip peripheral unit mode is set by writing to the I/O
register.
This section describes the CPU core’s operation modes. For operation modes of on-chip peripheral units, see the
chapters describing the various units.