NEC Network Controller uPD98502 - Manual (Page 500)

APPENDIX A MIPS III INSTRUCTION SET DETAILS
500 Preliminary User’s Manual S15543EJ1V0UM
JALX
Jump And Link Exchange
JALX
JALX
011101
31 26 25 0
6 26
target
Format:
JALX target
Description:
When a MIPS16 instruction can be executed, a 26-bit target is shifted to left by 2 bits and then added to higher 4
bits of the delay slot's address to make a target address. The program unconditionally jumps to the target address
with a delay of one instruction. The address of the instruction that follows the delay slot is stored to the link register
(r31). The ISA mode bit is inverted with a delay of one instruction. The value of bit 0 of the link register (r31)
indicates the ISA mode bit before jump.
Operation:
32 T: temp ← target
GPR [31] ← (PC + 8)
31..1
|| ISA MODE
T+1: PC ← PC
31..28 || temp || 0
2
64 T: temp ← target
GPR [31]
← (PC + 8)
63..1 || ISA MODE
T+1: PC ← PC
63..28 || temp || 0
2
ISA MODE toggle
ISA MODE toggle
Exceptions:
Reserved instruction exception (when MIPS16 instruction execution disabled)