NEC Network Controller uPD98502 - Manual (Page 131)

CHAPTER 2 V R 4120A
Preliminary User’s Manual S15543EJ1V0UM 131
2.5.3.1 Context register (4)
The Context register is a read/write register containing the pointer to an entry in the page table entry (PTE) array
on the memory; this array is a table that stores virtual-to-physical address translations. When there is a TLB miss, the
operating system loads the unsuccessfully translated entry from the PTE array to the TLB. The Context register is
used by the TLB Refill exception handler for loading TLB entries. The Context register duplicates some of the
information provided in the BadVAddr register, but the information is arranged in a form that is more useful for a
software TLB exception handler. Figure 2-47 shows the format of the Context register.
Figure 2-47. Context Register Format
(a) 32-bit mode
4 21 7
0
24
24 25 31 4 3
PTEBase BadVPN2 0
(b) 64-bit mode
4 21 39
0 25 63 4 3
PTEBase BadVPN2 0
PTEBase : The PTEBase field is a base address of the PTE entry table.
BadVPN2 : This field holds the value (VPN2) obtained by halving the virtual page number of the most recent
virtual address for which translation failed.
0 : RFU. Write 0 in a write operation. When this field is read, 0 is read.
The PTEBase field is used by software as the pointer to the base address of the PTE table in the current user
address space.
The 21-bit BadVPN2 field contains bits 31 to 11 of the virtual address that caused the TLB miss; bit 10 is excluded
because a single TLB entry maps to an even-odd page pair. For a 1-Kbyte page size, this format can directly address
the pair-table of 8-byte PTEs. When the page size is 4 Kbytes or more, shifting or masking this value produces the
correct PTE reference address.