NEC Network Controller uPD98502 - Manual (Page 232)

CHAPTER 4 ATM CELL PROCESSOR
232 Preliminary User’s Manual S15543EJ1V0UM
4.1.2.4 Other blocks
Work-RAM is 12 K-byte memory. Tables and Pool Descriptors are located in this RAM. It is shared between MCU
and UTOPIA Bus Controller block. It also can be accessed by V
R
4120A RISC Processor, using Indirect-Access.
4.1.3 ATM cell processing operation overview
In this section, only overview is described. Please refer to section 4.7 for more detailed information.
ATM Cell Processor supports AAL-5 SAR sublayer and ATM layer functions. This block provides LLC
encapsulation.
Figure 4-2. AAL-5 Sublayer and ATM Layer
C P C S P D U recovery
- C P C S -U U field notification
- C P I field notification
- packet length check & notific ation
- C R C check
C P C S P D U construction
C P C S P D U generation
- padding addition
- C P C S -U U field addition
- C P I field addition
- packet length calcuration & in sertion
- C R C -32 calcuration & insertion
D ividing a pacek t into ce lls
C ell processing & dem ultiplexing
- congestion indication
- cell payload type identificatio n
C ell processing & m ultip lexing
- cell scheduling
- cell header addition
U T O P IA
A A L-5
S A R S ublayer
A T M layer
V R 4120A R IS C P rocessor