NEC Network Controller uPD98502 - Manual (Page 10)

10 Preliminary User’s Manual S15543EJ1V0UM
3.4.15 SDRAM refresh............................................................................................................................219
3.4.16 Memory-to-CPU prefetch FIFO ....................................................................................................219
3.4.17 CPU-to-memory write FIFO .........................................................................................................219
3.4.18 SDRAM memory initialization ......................................................................................................220
3.5 IBUS Interface...........................................................................................................................221
3.5.1 Overview......................................................................................................................................221
3.5.2 Endian Conversion on IBUS master ............................................................................................221
3.5.3 Endian Conversion on IBUS slave ...............................................................................................222
3.5.4 ITCNTR (IBUS Timeout Timer Control Register) .........................................................................223
3.5.5 ITSETR (IBUS Timeout Timer Set Register)................................................................................223
3.6 DSU (Deadman’s SW Unit) ......................................................................................................224
3.6.1 Overview......................................................................................................................................224
3.6.2 DSUCNTR (DSU Control Register)..............................................................................................224
3.6.3 DSUSETR (DSU Time Set Register) ...........................................................................................224
3.6.4 DSUCLRR (DSU Clear Register).................................................................................................224
3.6.5 DSUTIMR (DSU Elapsed Time Register) ....................................................................................225
3.6.6 DSU register setting flow .............................................................................................................225
3.7 Endian Mode Software Issues ................................................................................................226
3.7.1 Overview......................................................................................................................................226
3.7.2 Endian modes ..............................................................................................................................226
CHAPTER 4 ATM CELL PROCESSOR.............................................................................................229
4.1 Overview ...................................................................................................................................229
4.1.1 Function features .........................................................................................................................229
4.1.2 Block diagram of ATM cell processor...........................................................................................230
4.1.3 ATM cell processing operation overview......................................................................................232
4.2 Memory Space ..........................................................................................................................236
4.2.1 Work RAM and register space .....................................................................................................237
4.2.2 Shared memory ...........................................................................................................................237
4.3 Interruption ...............................................................................................................................237
4.4 Registers for ATM Cell Processing ........................................................................................238
4.4.1 Register map ...............................................................................................................................238
4.4.2 A_GMR (General Mode Register)................................................................................................240
4.4.3 A_GSR (General Status Register) ...............................................................................................240
4.4.4 A_IMR (Interrupt Mask Register) .................................................................................................241
4.4.5 A_RQU (Receiving Queue Underrun Register) ...........................................................................242
4.4.6 A_RQA (Receiving Queue Alert Register) ...................................................................................242
4.4.7 A_VER (Version Register) ...........................................................................................................242
4.4.8 A_CMR (Command Register) ......................................................................................................242
4.4.9 A_CER (Command Extension Register) ......................................................................................242
4.4.10 A_MSA0 to A_MSA3 (Mailbox Start Address Register) ...............................................................243
4.4.11 A_MBA0 to A_MBA3 (Mailbox Bottom Address Register) ...........................................................243
4.4.12 A_MTA0 to A_MTA3 (Mailbox Tail Address Register) .................................................................243
4.4.13 A_MWA0 to A_MWA3 (Mailbox Write Address Register) ............................................................244
4.4.14 A_RCC (Valid Received Cell Counter).........................................................................................244
4.4.15 A_TCC (Valid Transmitted Cell Counter) .....................................................................................244
4.4.16 A_RUEC (Receive Unprovisioned VPI/VCI Error Cell Counter)...................................................244
4.4.17 A_RIDC (Receive Internal Dropped Cell Counter) .......................................................................244