NEC Network Controller uPD98502 - Manual (Page 193)

CHAPTER 3 SYSTEM CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 193
3.2.5 S_IMR (Interrupt Mask Register)
The interrupt mask register “S_IMR” is a read-write and 32-bit word-aligned register. S_IMR masks interruption for
each corresponding incident. A mask bit, which locates in the same bit location to a corresponding bit in S_ISR,
controls interruption triggered by the incident. If a bit of this register is reset to 0, the corresponding bit of the S_ISR is
masked. If it is set to 1, the corresponding bit is unmasked. When the unmask bit is set and the bit in S_ISR is set,
system controller asserts interrupt signal to V R 4120A. S_IMR is initialized to 0 at reset and contains the following
fields:
Bits Field R/W Default Description
31:5 Reserved R/W 0 Hardwired to 0.
4 WUIM R/W 0 Wakeup interrupt mask:
1 = unmask.
0 = mask.
3 EXTIM R/W 0 External interrupt mask:
1 = unmask.
0 = mask.
2 UARTIM R/W 0 UART interrupt mask:
1 = unmask.
0 = mask.
1 TM1IM R/W 0 Timer CH1 interrupt mask:
1 = unmask.
0 = mask.
0 TM0IM R/W 0 Timer CH0 interrupt mask:
1 = unmask.
0 = mask.
Remark MAC2 interrupt and PCI interrupt can not be masked by system controller.