NEC Network Controller uPD98502 - Manual (Page 293)

CHAPTER 5 ETHERNET CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 293
5.2.24 En_CAM1 (Carry Register 1 Mask Register)
This register masks the Interrupt that is generated from the setting of the bits in the En_CAR1 register.
Each mask bit can be enabled independently.
Bits Field R/W Default Description
31:16 Reserved R/W 0 Reserved for future use. Write 0s.
15 M1VT R/W 0 En_RVBT counter carry mask bit
14 M1UT R/W 0 En_TUCA counter carry mask bit
13 M1BT R/W 0 En_TBCA counter carry mask bit
12 M1MT R/W 0 En_TMCA counter carry mask bit
11 M1PT R/W 0 En_TPCT counter carry mask bit
10 M1TB R/W 0 En_TBYT counter carry mask bit
9 M1MX R/W 0 En_RMAX counter carry mask bit
8 M11K R/W 0 En_R1K counter carry mask bit
7 M1FE R/W 0 En_R511 counter carry mask bit
6 M1TF R/W 0 En_R255 counter carry mask bit
5 M1OT R/W 0 En_R127 counter carry mask bit
4 M1SF R/W 0 En_R64 counter carry mask bit
3 M1BR R/W 0 En_RBCA counter carry mask bit
2 M1MR R/W 0 En_RMCA counter carry mask bit
1 M1PR R/W 0 En_RPKT counter carry mask bit
0 M1RB R/W 0 En_RBYT counter carry mask bit