NEC Network Controller uPD98502 - Manual (Page 240)

CHAPTER 4 ATM CELL PROCESSOR
240 Preliminary User’s Manual S15543EJ1V0UM
4.4.2 A_GMR (General Mode Register)
A_GMR is used to select operation mode of this block, enables/disables ATM SAR operations. After reset,
V
R
4120A must write this register for initialization. Modification of A_GMR after starting Tx/Rx operations is prohibited.
All bits of this register are writeable, but the bits 31-15, 13-2 are reserved for future use. Initial value is all zero.
Bits Field R/W Default Description
31:15 Reserved R/W 0 Reserved for future use. Write ‘0’s.
14 LP R/W 0 0 = Loopback is not performed at the UTOPIA interface
1 = Loopback is performed at the UTOPIA interface
13:2 Reserved R/W 0 Reserved for future use. Write ‘0’s.
1 TE R/W 0 0 = Transmit disable
1 = Transmit enable
0 RE R/W 0 0 = Receive disable
1 = Receive enable
4.4.3 A_GSR (General Status Register)
A_GSR shows interruption status. When an event that triggers interruption occurs, F/W on RISC Core set a bit in
A_GSR corresponds to the type of event. If the corresponding bit in A_IMR (Interrupt Mask Register) is set to a ‘0’ and
the interruption is not masked, an interruption is issued to V
R
4120A. The bit in A_GSR is able to be read cleared.
When the same type of events occurs before the bit has been read, the bit will be set again.
Initial value is all zero.
Bits Field R/W Default Description
31 PI RC 0 0 = PHY layer device interruption has not occurred
1 = PHY layer device interruption has occurred
30 RQA RC 0 0 = receive Queue alert has not occurred
1 = receive Queue alert has occurred
29 RQU RC 0 0 = receive Queue underflow has not occurred
1 = receive Queue underflow has occurred
28:24 Reserved R 0 Reserved for future use
23 SQO RC 0 0 = scheduling Queue overflow has not occurred
1 = scheduling Queue overflow has occurred
22 Reserved R 0 Reserved for future use
21 FER RC 0 0 = Fatal Error has not occurred
1 = Fatal Error has occurred
20:17 Reserved R 0 Reserved for future use
16 BER RC 0 0 = Internal Bus Error has not occurred
1 = Internal Bus Error has occurred
15:8 RCR[7:0] RC 0 0 = raw cell is not in Pool No. [7:0]
1 = raw cell is in Pool No. [7:0]
7:4 MF[3:0] RC 0 0 = Mailbox No. [3:0] is not full
1 = Mailbox No. [3:0] is full
3:0 MM[3:0] RC 0 0 = mailbox No. [3:0] is not marked
1 = Mailbox No. [3:0] is marked