NEC Network Controller uPD98502 - Manual (Page 475)

APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM 475
DIV
Divide
DIV
rs
SPECIAL
0 0 0 0 0 0
rt
0
0 0 0 0 0 0 0 0 0 0
31 26 25 21 20 16 15 0
6 5 5 10
DIV
0 1 1 0 1 0
6 5
6
Format:
DIV rs, rt
Description:
The contents of general register rs are divided by the contents of general register rt, treating both operands as 2’s
complement values. No overflow exception occurs under any circumstances, and the result of this operation is
undefined when the divisor is zero.
In 64-bit mode, the operands must be valid sign-extended, 32-bit values.
This instruction is typically followed by additional instructions to check for a zero divisor and for overflow.
When the operation completes, the quotient word of the double result is loaded into special register LO, and the
remainder word of the double result is loaded into special register HI.
If either of the two preceding instructions is MFHI or MFLO, the results of those instructions are undefined. Correct
operation requires separating reads of HI or LO from writes by two or more instructions.
Operation:
32 T-2: LO ← undefined
HI ← undefined
T-1: LO ← undefined
HI ← undefined
T: LO ← GPR [rs] div GPR [rt]
HI ← GPR [rs] mod GPR [rt]
64 T-2: LO ← undefined
HI ← undefined
T-1: LO ← undefined
HI ← undefined
T: q ← GPR [rs]
31..0
div GPR [rt]
31..0
r ← GPR [rs]
31..0
mod GPR [rt]
31..0
LO ← (q
31
) 32 || q
31..0
HI ← (
r 31
)
32
|| r
31..0
Exceptions:
None