NEC Network Controller uPD98502 - Manual (Page 141)

CHAPTER 2 V R 4120A
Preliminary User’s Manual S15543EJ1V0UM 141
2.5.3.11 Cache error register (27)
The Cache Error register is a readable/writeable register. This register is defined to maintain software-compatibility
with the V
R
4100, and is not used in hardware because the V
R
4120A CPU has no parity.
Figure 2-59 shows the format of the Cache Error register.
Figure 2-59. Cache Error Register Format
32
0 31
0
0 : RFU. Write 0 in a write operation. When this field is read, 0 is read.
2.5.3.12 ErrorEPC register (30)
The Error Exception Program Counter (ErrorEPC) register is similar to the EPC register. It is used to store the
Program Counter value at which the Cache Error, Cold Reset, Soft Reset, or NMI exception has been serviced.
The read/write ErrorEPC register contains the virtual address at which instruction processing can resume after
servicing an error.
This address can be:
• Virtual address of the instruction that caused the exception.
• Virtual address of the immediately preceding branch or jump instruction, when the instruction associated with
the error exception is in a branch delay slot.
The contents of the ErrorEPC register do not change when the ERL bit of the Status register is set to 1. This
prevents the processor when other exceptions occur from overwriting the address of the instruction in this register
which causes an error exception.
There is no branch delay slot indication for the ErrorEPC register.
Figure 2-60 shows the format of the ErrorEPC register.
Figure 2-60. ErrorEPC Register Format
(a) 32-bit mode
32
0 31
ErrorEPC
(b) 64-bit mode
64
0 63
ErrorEPC
ErrorEPC: Program counter that indicates the restart address after Cold reset, Soft reset, or NMI exception.