Multu, Multiply unsigned – NEC Network Controller uPD98502 User Manual
Page 534
APPENDIX A MIPS III INSTRUCTION SET DETAILS
534
Preliminary User’s Manual S15543EJ1V0UM
MULTU
Multiply Unsigned
MULTU
rs
SPECIAL
0 0 0 0 0 0
MULTU
0 1 1 0 0 1
0
0 0 0 0 0 0 0 0 0 0
31
26 25
21 20
6 5
0
6
5
6
10
rt
5
16 15
Format:
MULTU rs, rt
Description:
The contents of general register
rs and the contents of general register rt are multiplied, treating both operands as
unsigned values. No overflow exception occurs under any circumstances.
In 64-bit mode, the operands must be valid 32-bit, sign-extended values.
When the operation completes, the low-order word of the double result is loaded into special register
LO, and the
high-order word of the double result is loaded into special register
HI.
If either of the two preceding instructions is MFHI or MFLO, the results of these instructions are undefined. Correct
operation requires separating reads of
HI or LO from writes by a minimum of two instructions.
Operation:
32
T-2:
LO
← undefined
HI
← undefined
T-1:
LO
← undefined
HI
← undefined
T:
t
← (0 || GPR [rs]) * (0 || GPR [rt])
LO
← t
31...0
HI
← t
63...32
64
T-2:
LO
← undefined
HI
← undefined
T-1:
LO
← undefined
HI
← undefined
T:
t
← (0 || GPR [rs]
31...0
) * (0 || GPR [rt]
31...0
)
LO
← (t
31
)
32
|| t
31...0
HI
← (t
63
)
32
|| t
63...32
Exceptions:
None