NEC Network Controller uPD98502 - Manual (Page 219)

CHAPTER 3 SYSTEM CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 219
3.4.15 SDRAM refresh
The system controller supports CAS-Before-RAS (CBR) DRAM refresh to all SDRAM address ranges. The refresh
clock is derived from the system clock; its rate is determined by programming the RCR filed in the SDRAM Refresh
Mode Register “SDRMR”.
The refresh logic requests access to SDRAM each time the counter reaches 0. The refresh logic can accumulate
up to a maximum of 15 refresh requests while it is waiting for the bus. Once the refresh logic owns the bus, all
accumulated refreshes are performed to system memory, and no other accesses (CPU or IBUS) are allowed.
Refreshes are staggered by one clock; that is, there will be at least one bus clock between transitions on any pair of
SDRASB signals. Refresh clears the system-memory prefetch FIFO automatically.
3.4.16 Memory-to-CPU prefetch FIFO
After each burst 4-words read, the memory controller prefetches 4 additional words into its internal prefetch FIFO. If
the processor subsequently attempts a read from an address immediately following (sequential to) the address of the
last read cycle, the first 4 words will supplied from the prefetch FIFO.
The memory controller compares the current SysAD address with the previous address to determine the sequential
nature of the access. Prefetched words are retained in the prefetch FIFO if accesses to resources other than system
memory are performed between system memory accesses.
3.4.17 CPU-to-memory write FIFO
The memory controller has a 4-word CPU-to-memory write FIFO. This FIFO accepts writes at the maximum CPU
speed. A single address is held for the buffered write, allowing the buffering of a single write transaction. That
transaction may be a word, double word, 4-word data-cache write-back. When a word is placed in the FIFO by the
CPU, the memory controller attempts to write the FIFO’s contents to memory as quickly as possible. If the next CPU
read or write is addressed to memory, the controller negates ready signal, thus causing the next CPU transaction
(read or write) to stall until the controller empties its FIFO. If the next CPU transaction (read or write) is addressed to a
IBUS target, the memory controller asserts ready signal, thus the CPU transaction to complete.