NEC Network Controller uPD98502 - Manual (Page 57)

Preliminary User’s Manual S15543EJ1V0UM 57
CHAPTER 2 V
R
4120A
Caution The µµµµPD98502 doesn’t support MIPS16 instructions.
This chapter describes an V R 4120A RISC Processor Core operation (MIPS instruction, Pipeline, etc.). Following in
this Document, it is call for V R 4120A RISC Processor Core with “V R 4120A” or “V R 4120A Core” simply.
2.1 Overview for V
R
4120A
Figure 2-1 shows the internal block diagram of the V R 4120A core.
In addition to the conventional high-performance integer operation units, this CPU core has the full-associative
format translation look aside buffer (TLB), which has 32 entries that provide mapping to 2-page pairs (odd and even)
for one entry. Moreover, it also has instruction caches, data caches, and bus interface.
Figure 2-1. V
R
4120A Core Internal Block Diagram
CPU CP0 Instruction
Cache
16 Kbyte
Data
Cache
8 Kbyte
Bus
Interface
Clock
Generator
Address/Data(o)
Address/Data(i)
ID bus
VA bus
Control(o)
Control(i)
TLB
System
Controller
V R 4120A Core