NEC Network Controller uPD98502 - Manual (Page 519)

APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM 519
LWR
Load Word Right (2/3)
LWR
The contents of general register rt are internally bypassed within the processor so that no NOP is needed between
an immediately preceding load instruction which specifies register rt and a following LWR (or LWL) instruction
which also specifies register rt.
No address error exceptions due to alignment are possible.
Operation:
32 T: vAddr
← ((offset
15
)
16
|| offset
15...0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE - 1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
if BigEndianMem = 1 then
pAddr
← pAddr
PSIZE - 1...3
|| 0
3
endif
byte ← vAddr
1...0
xor BigEndianCPU
2
word ← vAddr
2
xor BigEndianCPU
mem ← LoadMemory (uncached, 0 || byte, pAddr, vAddr, DATA)
temp ← GPR [rt]
31...32 – 8 * byte
|| mem
31 + 32 * word...32 * word + 8 * byte
GPR [rt] ← temp
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE - 1...3
|| (pAddr
2...0
xor ReverseEndian
3
)
if BigEndianMem = 1 then
pAddr ← pAddr
PSIZE - 1...3
|| 0
3
endif
byte ← vAddr
1...0
xor BigEndianCPU
2
word
← vAddr
2
xor BigEndianCPU
mem ← LoadMemory (uncached, WORD-byte, pAddr, vAddr, DATA)
temp ← GPR [rt]
31...32 – 8 * byte
|| mem
31 + 32 * word...32 * word + 8 * byte
GPR [rt] ← (temp
31
)
32
|| temp