NEC Network Controller uPD98502 - Manual (Page 381)

CHAPTER 7 PCI CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 381
7.2.3 Abnormal Termination
7.2.3.1 On PCI bus
(1) Detecting parity error
When the access to the PCI Controller is issued on PCI bus and the PCI Controller detects the address parity error
as a target, the PCI Controller issues a target abort to terminate the access. At the same time, the PCI Controller sets
“Detected Parity Error” bit in configuration register, PPERR bit in P_IGSR register and DPERR bit in P_PGSR
register, and issues interrupts to an external PCI-Host device and the V R 4120A (if not masked). When “Parity Error
Response” bit and “SERR# Enable” bit are set to “1”, the PCI Controller asserts SERR_B signal and set “signaled
SERR_B” bit in configuration register (please note that in this case this wrong Address data is passed through the
IBUS).
When the access to the PCI Controller is issued on PCI bus and the PCI Controller detects the data parity error as
target, the PCI Controller sets following bits; “Detected Parity Error” bit in configuration register, PPERR bit in P_IGSR
register and DPERR bit in P_PGSR register. In addition, the PCI Controller issues interrupts to an external PCI-Host
device and the V R 4120A (if not masked) too. However, the PCI Controller does not terminate the current transfer, and
continues it.
When the PCI Controller issues the access on PCI bus and the PCI Controller detects the data parity error as
master, the PCI Controller sets following bits; “Detected Parity Error” bit in configuration register, PPERR bit in
P_IGSR register and DPERR bit in P_PGSR register. In addition, the PCI Controller issues interrupts to an external
PCI-Host device and the V R 4120A (if not masked). When “Parity Error Response” bit in configuration register is set,
the PCI Controller asserts PERR# signal and set “Master Data Parity Error” bit in configuration register. However, the
PCI Controller does not terminate the current transfer, and continues it.
(2) Received master abort as PCI-master
When the PCI Controller receives master abort on PCI bus as master, the PCI Controller sets “Received Master
Abort” bit in configuration register, RMABT bit in P_PGSR register. In addition, the PCI Controller sets RDMAT bit in
P_IGSR register when read transaction, or sets WRMAT bit in P_IGSR register when write transaction. Then the PCI
Controller issues interrupts to an external PCI-Host device and the V R 4120A (if not masked). The PCI Controller stops
the access, and returns to the state in which the PCI Controller can accept a new access.
(3) Received target abort as PCI-master
When the PCI Controller receives target abort on PCI bus as master, the PCI Controller sets “Received Target
Abort” bit in configuration register and RTABT bit in P_PGSR register. In addition, the PCI Controller sets RDTAT bit
in P_IGSR register when read transaction, or sets WRTAT bit in P_IGSR register when write transaction. Then the
PCI Controller issues interrupts to an external PCI-Host device and the V R 4120A (if not masked). The PCI Controller
stops the access, and returns to the state in which the PCI Controller can accept a new access.
(4) Received target disconnect as PCI-master
When the PCI Controller receives target disconnect on PCI bus as master, the PCI Controller terminates the
current access and issues the access to the same target again in order to transfer remains of data.
(5) Received target retry as PCI-master
When the PCI Controller receives target retry on PCI bus as master, the PCI Controller terminates the current
access and issues the access to the same target again in order to transfer data.