NEC Network Controller uPD98502 - Manual (Page 256)

CHAPTER 4 ATM CELL PROCESSOR
256 Preliminary User’s Manual S15543EJ1V0UM
4.6.2 After RISC core’s F/W is starting
RISC Core starts its operation from address xx00_0000H. When it starts fetching an instruction located in address
xx00_0000H, a dedicated H/W will stop RISC Core and will copy a block of instructions. This copy operation will be
handled in the same manner as I-cache replacement.
Lower 8 KB of Instruction space in RISC Core will be copied on Instruction RAM because it will contain interruption
vector table. The other part of the space is accessed through 8 KB of Instruction cache. In case that the total size of
F/W is smaller than 16 KB, RISC Core can run fastest because once all necessary instruction code is copied in, no
cache miss will occur.
Figure 4-17. Instruction RAM and Instruction Cache
IR AM
(8 K B )
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I-C ache
(8 K B)
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opy
00 _00 00H
F /W
Int. T able
0F_ FFFFH
00 _20 00H
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Copy
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opy
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