NEC Network Controller uPD98502 - Manual (Page 268)

CHAPTER 4 ATM CELL PROCESSOR
268 Preliminary User’s Manual S15543EJ1V0UM
Word0 Identical to the contents of Word0 in the packet descriptor in system memory. The
initial value must be all zeros. ATM Cell copies the Word0 in the packet descriptor
into this field.
L This bit is used internally for SAR processing. The initial value must always be a 1.
PRIORITY Specifies send priority.
111: CBR
110: VBR
010: UBR
VPI/VCI VPI/VCI values to be contained in the cell header
No. OF BYTES TRANSMITTED
IN THIS PACKET
Number of bytes in the packet that have been sent so far. The initial value is 0.
REMAINING BYTES IN
CURRENT BUFFER
Number of bytes in the current buffer that have not been sent. The initial value is 0.
CRC-32 COUNT CRC-32 value calculated for the transmitted cells of this packet. The final CRC-32
value is set in the CRC-32 field in the trailer.
BUFFER READ ADDRESS Pointer to the byte in the current buffer that is to be transferred next Tx time.
NEXT BUFFER ADDRESS Pointer to the next buffer in the current packet directory
MBS0 Maximum Burst Size. The number of cells continuously transmitted with PCR. Only
used in VBR mode.
MBS Internally used for counting MBS0. Initially, the same value as MBS0 has to be set.
Only used in VBR mode.
PHY No. The number of the PHY which cells that belongs to this VC transmits to.
A "Active" bit indicating whether the VC table is in the active or idle state.
1: Active state
0: Idle state
MCR Minimum Cell Rate. In VBR mode, SCR has to be set in this field.
PCR Peak Cell Rate.
Word 10 These fields are used internally for scheduling use.
Word 11 & Word 12 These fields are used internally.
FIRST PACKET INFO The start address of the first Packet Info structure in transmit queue for this VC.
The initial value has to be 0.
LAST PACKET INFO The start address of the last Packet Info structure in transmit queue for this VC.
The initial value has to be 0.
4.8.2.3 Non AAL-5 traffic support
(1) OAM F5 cell transmission
When host sets OAM F5 cell pattern (100 and 101) in the PTI field in packet descriptor, ATM Cell Processor
doesn’t add AAL-5 trailer. In this case, even though host sets more than 48 bytes in “SIZE” field in the packet
descriptor, ATM Cell Processor only reads 48 bytes from the top of the data buffer and ignores the data after that. If
host sets the bytes less than 48 byte in “SIZE” field, ATM Cell Processor adds padding. For OAM F5 cell transmission,
host has to set different packet descriptor for each OAM F5 cell.
For OAM F5 cell transmission, ATM Cell Processor inserts CRC-10, if host sets “C10 bit” to 1 in packet descriptor.
ATM Cell Processor calculates CRC-10 for 46 bytes and 6 bits and overwrites the result to the last 10 bits in the
payload.
In addition, F/W for ATM Cell Processor supports Forward Monitoring and Backward Reporting functions. The
detail of the functions will be announced.