NEC Network Controller uPD98502 - Manual (Page 379)

CHAPTER 7 PCI CONTROLLER
Preliminary User’s Manual S15543EJ1V0UM 379
7.2.2.4 Read issue from PCI to internal bus
(1) Delayed read transaction
When PDRTD bit in P_BCNT register is ‘0’, the PCI Controller uses “Delayed Read Transaction” rule for read
transactions from Internal bus-side to PCI-side. The rule is as follows;
<1> A PCI master device issues the read transaction to an internal bus target block.
<2> The PCI Controller responds to this access and issues “retry” to PCI master device. However, the PCI
Controller latches the address and the command, and remembers the access issued. Then, the PCI
Controller issues “retry” to all read access until the transaction on internal bus has been completed.
<3> The PCI Controller issues the read transaction to internal bus target block
<4> The internal bus target block accepts this access and the PCI Controller reads data into the internal FIFO
from the internal bus target block.
<5> The PCI Controller waits that the same access that is issued comes on PCI bus. To other accesses, the PCI
Controller issues “retry”.
<6> When the same access comes, which means the access with the same address and the same command,
the PCI Controller accepts this access and returns the data in the internal FIFO.
Figure 7-8. Delayed Read Transaction from PCI to Internal bus
PCI
Controller
PCI
Master
Device
Internal
Bus Block
<1>
<4>
<2>
<3>
<5>
<6>
As the issued burst size cannot be known until the transaction is completed, the PCI Controller decides the
prefetched word size based on the issued PCI command when Cache-Line-Size is valid. When Memory-Read
command is used, the prefetched word size is 1 word. When Memory-Read-Line command, the size is same as
Cache-Line-Size, when Memory-Read-Multiple command, the prefetched size is 16 words. When Cache-Line-Size is
not valid, the prefetched size is always 16 words. When the PCI master device issues more words, the PCI Controller
terminates the transaction by “disconnect” after it returns the prefetched data to PCI master device. When the PCI
Controller encounters the address boundary, it issues “disconnect”, too.
If the same access with that has been issued does not come within 2 15 clocks, the PCI Controller discards the data
in the internal FIFO, sets IFDSC bit of P_IGSR register and issues an interrupt to the V R 4120A by (if not masked).
When the PCI Controller receives Bus Error on internal bus after it accepts delayed-read from PCI-side, it sets
IRBER bit of P_IGSR register and PRBER bit of P_PGSR register, and issues interrupts to an external PCI-Host
device and the V
R
4120A (if not masked). Then, the PCI Controller issues “target abort” responding to the access from
PCI Master Device.