Load doubleword right (1/3) – NEC Network Controller uPD98502 User Manual
Page 508
APPENDIX A MIPS III INSTRUCTION SET DETAILS
508
Preliminary User’s Manual S15543EJ1V0UM
LDR
Load Doubleword Right (1/3)
LDR
base
LDR
0 1 1 0 1 1
rt
offset
31
26 25
21 20
16 15
0
6
5
5
16
Format:
LDR rt, offset (base)
Description:
This instruction can be used in combination with the LDL instruction to load a register with eight consecutive bytes
from memory, when the bytes cross a doubleword boundary. LDL instruction loads the high-order portion of data
and LDR instruction loads the low-order portion of data.
The LDR instruction adds its sign-extended 16-bit
offset to the contents of general register base to form a virtual
address that can specify an arbitrary byte. It reads bytes only from the doubleword in memory that contains the
specified starting byte. From one to eight bytes will be loaded, depending on the starting byte specified.
Conceptually, it starts at the specified byte in memory and loads that byte into the low-order (right-most) byte of the
register; then it loads bytes from memory into the register until it reaches the high-order byte of the doubleword in
memory. The most significant (left-most) byte(s) of the register will not be changed.
address 8
address 0
memory
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
A
B
C
D
E
F
G
H
A
B
C
D
E
7
6
5
before
after
$24
$24
register
LDR $24, 5 ($0)
register