Tlbwi, Write indexed tlb entry – NEC Network Controller uPD98502 User Manual
Page 578
APPENDIX A MIPS III INSTRUCTION SET DETAILS
578
Preliminary User’s Manual S15543EJ1V0UM
TLBWI
Write Indexed TLB Entry
TLBWI
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
COP0
0 1 0 0 0 0
TLBWI
0 0 0 0 1 0
31
26 25
6 5
0
6
19
6
CO
1
1
24
Format:
TLBWI
Description:
The TLB entry pointed at by the contents of the TLB Index register is loaded with the contents of the EntryHi and
EntryLo registers.
The
G bit of the TLB is written with the logical AND of the G bits in the EntryLo0 and EntryLo1 registers.
The operation is invalid (and the results are unspecified) if the contents of the TLB Index register are greater than
the number of TLB entries in the processor.
Operation:
32, 64 T:
TLB [Index
5...0
]
←
PageMask || (EntryHi and not PageMask) || EntryLo1 || EntryLo0
Exceptions:
Coprocessor unusable exception