NEC Network Controller uPD98502 - Manual (Page 592)

APPENDIX B V R 4120A COPROCESSOR 0 HAZARDS
592 Preliminary User’s Manual S15543EJ1V0UM
Remarks 1. The instruction following MTC0 must not be MFC0.
2. The five instructions following MTC0 to Status register that changes KSU and sets EXL and ERL
may be executed in the new mode, and not kernel mode. This can be avoided by setting EXL first,
leaving KSU set to kernel, and later changing KSU.
3. There must be two non-load, non-CACHE instructions between a store and a CACHE instruction
directed to the same primary cache line as the store.
The status during execution of the following instruction for which CP0 hazards must be considered is described
below.
(1) MTC0
Destination: The completion of writing to a destination register (CP0) of MTC0.
(2) MFC0
Source: The confirmation of a source register (CP0) of MFC0.
(3) TLBR
Source: The confirmation of the status of TLB and the Index register before the execution of TLBR.
Destination: The completion of writing to a destination register (CP0) of TLBR.
(4) TLBWI, TLBWR
Source: The confirmation of a source register of these instructions and registers used to specify a
TLB entry.
Destination: The completion of writing to TLB by these instructions.
(5) TLBP
Source: The confirmation of the PageMask register and the EntryHi register before the execution of
TLBP.
Destination: The completion of writing the result of execution of TLBP to the Index register.
(6) ERET
Source : The confirmation of registers containing information necessary for executing ERET.
Destination : The completion of the processor state transition by the execution of ERET.
(7) CACHE Index Load Tag
Destination: The completion of writing the results of execution of this instruction to the related registers.
(8) CACHE Index Store Tag
Source: The confirmation of registers containing information necessary for executing this instruction.
(9) Coprocessor Usable Test
Source: The confirmation of modes set by the bits of the CP0 registers in the "Source" column.
Examples 1. When accessing the CP0 registers in User mode after the contents of the CU0 bit of the
Status register are modified, or when executing an instruction such as TLB instructions,
CACHE instructions, or branch instructions that use the resource of the CP0.
2. When accessing the CP0 registers in the operating mode set in the Status register after the
KSU, EXL, and ERL bits of the Status register are modified.