NEC Network Controller uPD98502 - Manual (Page 521)

APPENDIX A MIPS III INSTRUCTION SET DETAILS
Preliminary User’s Manual S15543EJ1V0UM 521
LWU
Load Word Unsigned
LWU
base
LWU
1 0 1 1 1 1
rt offset
31 26 25 21 20 16 15 0
6 5 5 16
Format:
LWU rt, offset (base)
Description:
The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address.
The contents of the word at the memory location specified by the effective address are loaded into general register
rt. The loaded word is zero-extended.
If either of the two least-significant bits of the effective address is non-zero, an address error exception occurs.
This operation is defined in 64-bit mode or in 32-bit kernel mode. Execution of this instruction in 32-bit user or
supervisor mode causes a reserved instruction exception.
Operation:
32 T: vAddr ← ((offset
15
) 16 || offset
15...0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr ← pAddr
PSIZE - 1...3
|| (pAddr
2...0
xor (ReverseEndian || 0 2 ))
mem ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
byte ← vAddr
2...0
xor (BigEndianCPU || 0 2 )
GPR [rt] ← 0 32
|| mem 31 + 8 * byte...8 * byte
64 T: vAddr ← ((offset
15
)
48
|| offset
15...0
) + GPR [base]
(pAddr, uncached) ← AddressTranslation (vAddr, DATA)
pAddr
← pAddr
PSIZE - 1...3
|| (pAddr
2...0
xor (ReverseEndian || 0
2
))
mem ← LoadMemory (uncached, WORD, pAddr, vAddr, DATA)
byte
← vAddr
2...0
xor (BigEndianCPU || 0 2 )
GPR [rt] ← 0 32
|| mem
31 + 8 * byte...8 * byte
Exceptions:
TLB refill exception
TLB invalid exception
Bus error exception
Address error exception
Reserved instruction exception (32-bit user mode/supervisor mode)