NEC Network Controller uPD98502 - Manual (Page 576)

APPENDIX A MIPS III INSTRUCTION SET DETAILS
576 Preliminary User’s Manual S15543EJ1V0UM
TLBP
Probe TLB For Matching Entry
TLBP
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
COP0
0 1 0 0 0 0
TLBP
0 0 1 0 0 0
31 26 25 6 5 0
6 19 6
CO
1
1
24
Format:
TLBP
Description:
The Index register is loaded with the address of the TLB entry whose contents match the contents of the EntryHi
register. If no TLB entry matches, the high-order bit of the Index register is set.
The architecture does not specify the operation of memory references associated with the instruction immediately
after a TLBP instruction, nor is the operation specified if more than one TLB entry matches.
Operation:
32 T: Index ← 1 || 0 25
|| Undefined
6
for i in 0...TLBEntries - 1
if (TLB [i]
95...77
= EntryHi
31...13
) and (TLB [i]
76
or
(TLB [i]
71...64
= EntryHi
7...0
)) then
Index ← 0 26
|| i
5...0
endif
endfor
64 T: Index ← 1 || 0 25
|| Undefined
6
for i in 0...TLBEntries - 1
if (TLB [i]
167...141
and not (0
15
|| TLB [i]
216...205
))
= (EntryHi
39...13
) and not (0 15 || TLB [i]
216...205
)) and
(TLB [i]
140
or (TLB [i]
135...128
= EntryHi
7...0
)) then
Index ← 0 26 || i
5...0
endif
endfor
Exceptions:
Coprocessor unusable exception