NEC Network Controller uPD98502 - Manual (Page 224)

CHAPTER 3 SYSTEM CONTROLLER
224 Preliminary User’s Manual S15543EJ1V0UM
3.6 DSU (Deadman’s SW Unit)
3.6.1 Overview
The DSU detects when the V
R
4120A is in runaway (endless loop) state and resets the V
R
4120A. The use of the
DSU to minimize runaway time effectively minimizes data loss that can occur due to software-related runaway states.
3.6.2 DSUCNTR (DSU Control Register)
This register is used to enable use of the Deadman’s Switch functions.
DSUCNTR is a 32-bit word-aligned register. Default is 0H.
Bits Field R/W Default Description
31:1 Reserved R/W 0 Hardwired to 0.
0 DSWEN R/W 0 Deadman’s Switch function enable
1 = enable
0 = disable
3.6.3 DSUSETR (DSU Time Set Register)
This register sets the Deadman’s Switch cycle. The Deadman’s Switch cycle can be set in 1-clock increments in a
range from 1 to 2 32 – 1 clock. The DSUCLRR’s DSWCLR bit must be set by means of software within the specified
cycle time. DSUSETR is a 32-bit word-aligned register. Default is 8000_0000H.
Bits Field R/W Default Description
31:0 DEDTIM R/W 8000_
0000H
Deadman’s Switch cycle setting
DSU cycle = DEDTIME value system clock period
(100 MHz:10 ns, 66 MHz:15 ns)
example:
DEDTIM = 05F5_E100H (100 MHz) or 03F9_40AAH (66 MHz)
-> DSU cycle = 1 sec
DEDTIM = 0BEB_C200H (100 MHz) or 07F2_8154H (66 MHz)
-> DSU cycle = 2 sec
DEDTIM = 11E1_A300H (100 MHz) or 0BEB_C200H (66 MHz)
-> DUS cycle = 3 sec
: : :
3.6.4 DSUCLRR (DSU Clear Register)
Setting the DSWCLR bit in this register to ‘1’ clears the Deadman’s Switch counter. The V
R
4120A is reset
automatically if a ‘1’ is not written to the bit within the period specified in DSUSETR. DSUCLR is a 32-bit word-aligned
register. Default is 0H.
Bits Field R/W Default Description
31:1 Reserved W 0 Hardwired to 0.
0 DSWCLR W 0 Deadman’s Switch counter clear. Cleared to 0 when 1 is written.
1 = Clear
0 = Don’t clear